About the CHERI Alliance

The CHERI Alliance is a UK-based industry and academic initiative founded to promote the global adoption of Capability Hardware Enhanced RISC Instructions (CHERI), a proven hardware-software co-design technology that significantly enhances memory safety and system security. Launched by founding members lowRISC and SCI Semiconductor, the Alliance builds on over a decade of pioneering research from the University of Cambridge and SRI International.

CHERI introduces fine-grained capabilities to conventional processor instruction sets, enabling spatial memory protection, hardware-enforced compartmentalization, and mitigation of entire classes of common vulnerabilities. The CHERI Alliance serves as a collaboration forum and standards body, working with semiconductor companies, OS developers, research institutions, and public-sector stakeholders to guide specification, tooling, and ecosystem adoption.

The Alliance is actively engaged in bringing CHERI to mainstream processor architectures and accelerating the deployment of hardware-enforced security in commercial computing platforms.

Learn more at www.cheri-alliance.org.


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Molly Bakewell Chamberlin
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