lowRISC C.I.C., the open silicon ecosystem organisation, together with SCI Semiconductor, a leader in CHERI solutions, today announced the release of the open-source Sunburst Chip design repository. The release marks a key milestone in phase two of the DSbD/UKRI-funded Sunburst Project (Grant Number: 107540), and supports the commercialisation of CHERIoT-Ibex based secure microcontrollers, including SCI’s upcoming ICENI device family.
CHERI (Capability Hardware Enhanced RISC Instructions) technology addresses memory safety vulnerabilities that account for approximately 70% of reported exploits, making it a critical advancement for industries requiring secure and efficient embedded systems.
“By addressing security challenges in a ‘by design’ manner, CHERIoT-Ibex has proven its potential as a next-generation secure microcontroller architecture. However, to move the needle, CHERIoT-based IP must be both commercial-grade and readily available,” said Dr. Gavin Ferris, CEO of lowRISC. “Our release, with SCI, of the permissively licensed open source Sunburst Chip repository is a significant turning point in bringing CHERI-based security to the embedded systems market, and represents a core deliverable of the Sunburst project.”
This news follows lowRISC and SCI Semiconductor’s commitment to tape out the Sonata™ design (incorporating Microsoft’s Ibex®-based CHERIoT core). This builds on the success of the first phase of the Sunburst Project, which introduced CHERI technology to embedded engineers through the Sonata™ FPGA board and RTL platform. The project was subsequently extended to deliver an open source SoC top-level, reusing much of the IP developed for OpenTitan “Earl Grey”, which itself has reached production with Google and is heading into Chromebooks this year. Sonata™ platforms distributed to key stakeholders by the Sunburst project are driving awareness, technical engagement and innovation around memory-safe microcontrollers as could be seen in the recent Digital Catapult / DSbD TAP Cohort 6 event.
SCI Semiconductor is using the Sunburst Chip repository as the foundation for its ICENI family of secure microcontrollers. These are being developed on a 22nm commercial process, and will drive this design to form the basis for the first ICENI secure microcontroller, a commercial chip available in the second half of 2025.
“The availability of commercial-grade CHERI technology is a key factor in shaping the future of secure computing,” said Haydn Povey, Chief Executive, SCI Semiconductor. “We are on a mission to ensure that the market has access to robust, open source foundations for secure-by-design microcontrollers enabling a focus on differentiation, just as we have with Iceni.”
The Sunburst Chip repository is publicly available at: https://github.com/lowRISC/sunburst-chip. Developers and researchers are encouraged to explore the repository and leverage the technology for their own CHERIoT-Ibex based designs. Sonata™ FPGA boards incorporating CHERIoT-Ibex technology are available for purchase via Mouser Electronics.
About lowRISC
Founded in 2014 at the University of Cambridge, lowRISC is a not-for-profit company focused on collaborative open silicon development. It provides long-term infrastructure and engineering support for projects like OpenTitan and Sunburst, advancing secure and open source silicon through its Silicon Commons® approach. To learn more, please click here.
About SCI Semiconductor
SCI Semiconductor was established to commercialise CHERI-enabled devices. With a team of industry veterans in processor IP, chip design, and high-integrity software, SCI focuses on delivering secure and high-performance computing solutions for critical applications. For more information, please click here.
About the CHERI Alliance
lowRISC and SCI Semiconductor are founding members of the CHERI Alliance, promoting the global adoption of the Capability Hardware Enhanced RISC Instructions (CHERI) security technology across the computing industry. Building on over a decade of pioneering research by the University of Cambridge and SRI International, CHERI introduces a proven architecture designed to enhance system security through fine-grained memory protection and software compartmentalization. The Alliance is actively engaging with industry, academia, and the public sector to standardise and implement CHERI across a diverse range of computing platforms. To learn more, visit http://www.cheri-alliance.org
Source/Photo Credit: lowRISC and SCI Semiconductor
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